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SP5769
3GHz I2C Bus Synthesiser Preliminary information
DS4878 Issue 4.0 October 1999
Features
G Complete 3*0 GHz Single Chip System G Optimised for Low Phase Noise, with Comparison G G G G G G G G G G G
Ordering Information
SP5769A/KG/MP1S (Tubes) SP5769A/KG/MP1T (Tape and Reel) SP5769A/KG/QP1S (Tubes) SP5769A/KG/QP1T (Tape and Reel) size equal to the loop comparison frequency and no prescaler phase noise degradation over the full RF operating range. The comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. The oscillator frequency, fREF, or phase comparator frequency, fCOMP, can be switched to the REF/ COMP output providing a reference for a second frequency synthesiser. The synthesiser is controlled via an 12C bus
Frequencies up to 4 MHz No RF Prescaler Selectable Reference Division Ratio Selectable Reference/Comparison Frequency Output Selectable Charge Pump Current with 10:1 Ratio Four Selectable I2C Addresses I2C Fast Mode Compliant with 3*3V and 5V Logic Levels Four Switching Ports Functional Replacement for SP5659 (except ADC) Pin Compatible with SP5655 Power Consumption 110mW with VCC = 5*5V, all Ports off ESD Protection 2kV min., MIL-STD-883B Method 3015 Cat.1 (Normal ESD handling procedures should be observed)
Absolute Maximum Ratings
All voltages are referred to VEE = 0V Supply voltage, VCC 0*3V to 17V RF differential input voltage 2*5Vp-p All I/O port DC offsets 20*3 to VCC 10*3V SDA and SCL DC offset 20*3 to 6V Storage temperature 255C to 1125C Junction temperature 1150C MP16 thermal resistance Chip to ambient, JA 80C/W Chip to case, JC 20C/W
Applications
G Digital Satellite and Cable Tuning Systems G Communications Systems
The SP5769 is a single chip frequency synthesiser designed for tuning systems up to 3GHz. The RF preamplifier interfaces direct with the RF programmable divider, which is of MN1A construction so giving a step
11 ENABLE/ SELECT 13 2
REF/COMP CRYSTAL CAP
RF INPUT
11-BIT COUNT
REFERENCE DIVIDER
3
14
416/17
4-BIT COUNT
LOCK fPD/2
CRYSTAL CHARGE PUMP DRIVE
1
PUMP
16 CP TEST MODE SET
15-BIT LATCH ADDRESS SDA SCL
10 4 5
2 BIT
4 BIT
2 BIT
3 BIT
I2C BUS TRANSCEIVER 4-BIT LATCH AND PORT INTERFACE
6 7 8 9 fPD/2 SELECT
P3
P2
P1
P0
Figure 1 SP5769 block diagram
SP5769
CHARGE PUMP CRYSTAL CAP CRYSTAL SDA SCL PORT P3/LOGLEV PORT P2 PORT P1
1 2 3 4 5 6 7 8
16 15 14
SP 5769
13 12 11 10 9
DRIVE VEE RF INPUT RFINPUT VCC REF/COMP ADDRESS PORTP0
CHARGE PUMP CRYSTAL CAP CRYSTAL SDA SCL PORT P3/LOGLEV PORT P2 PORT P1
1 2 3 4 5 6 7 8
16 15 14
SP 5769
13 12 11 10 9
DRIVE VEE RF INPUT RFINPUT VCC REF/COMP ADDRESS PORTP0
MP16
Figure 2 Pin connections - top view
QP16
Electrical Characteristics
Test conditions (unless otherwise stated): TAMB = 240C to 180C, VCC = 4*5V to 5*5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Supply current RF input Input voltage Input impedance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Input hysteresis SDA output voltage SCL clock rate Charge pump Output current Output leakage Drive output current Crystal frequency External reference Input frequency Drive level Buffered REF/COMP Output amplitude Output impedance Comparison frequency Equivalent phase noise at phase detector RF division ratio Reference division ratio Pin 12 13,14 100 40 4,5 3 2*3 0 0 5*5 5*5 1*5 1 10 210 10 0*4 0*6 400 V V V V A A A V V V kHz 5V I2C logic selected 3*3V I2C logic selected 5V I2C logic selected 3*3V I2C logic selected Input voltage = VCC Input voltage = VEE VCC = VEE ISINK = 3mA ISINK = 6mA Min. Typ. 20 Max. 25 300 300 Units mA mVrms 100MHz to 200MHz mVrms 200MHz to 3GHz See Figure 4 Conditions
0*4 4 5 1 1 16 2,3 3
63 0*5 2 2 0*2
610 20 20 0*5
nA mA MHz MHz Vp-p
See Table 6, VPIN1 = 2V VPIN1 = 2V, VCC = 15*0V, TAMB = 25C VPIN16 = 0*7V See Figure 5 for application Sinewave coupled via 10nF blocking capacitor Sinewave coupled via 10nF blocking capacitor AC coupled, see Note 2 0*0625 to 20MHz Enabled by bit RE = 1
11 0*35 250 4 2148 240 32767
Vp-p MHz dBc/Hz SSB, within loop bandwidth, all comparison frequencies See Table 1 cont...
2
SP5769 Electrical Characteristics (continued)
Value Characteristic Output Ports P3 - P0 Sink current Leakage current Address select Input high current Input low current Logic level select Input high level Input low level Input current Pin 6-9 2 10 10 1 20*5 6 3 0 1*5 10 V V A mA A mA A VPORT = 0*7V VPORT = VCC See Note 1 See Table 3 VIN = VCC VIN = VEE See Note 3 5V I2C logic level selected or open circuit 3*3V I2C logic level selected VIN = VEE to VCC Min. Typ. Max. Units Conditions
NOTES 1. Output ports high impedance on power-up, with SDA and SCL at logic `0'. 2. If the REF/COMP output is not used, the output should be left open circuit or connected to VCC and disabled by setting RE = `0'. 3. Bi-dectional port. When used as an output, the input logic state is ignored. When used as an input, the port should be switched into high impedance (off) state.
Functional Description
The SP5769 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varactor tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces with the 15-bit fully programmable divider which is of MN1A architecture, where the dual modulus prescaler is 416/17, the A counter is 4 bits, and the M counter is 11 bits. The output of the programmable divider is applied to the phase comparator where it is compared in both phase and frequency domains with the comparison frequency. This frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 16 ratios as detailed inTable 1. The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. The programmable divider output fPD/2 can be switched to port P0 by programming the device into test mode. The test modes are described inTable 5. Programming The SP5769 is controlled by an I2C data bus and is compatible with both standard and fast mode formats and with I2C data generated from nominal 3*3V and 5V sources. The I2C logic level is selected by the bi-directional port P3/ LOGLEV. 5V logic levels are selected by connecting P3/ LOGLEV to VCC or leaving it open circuit; 3*3V logic levels are set by connecting P3/LOGLEV to ground. If this port is used as an input the P3 data should be programmed to high impedance. If used as an output only 5V logic levels can be used, in which case the logic state imposed by the port on the input is ignored. Data and clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format . The synthesiser can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 2 and 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C bus system. Table 4 shows how the address is selected by applying a voltage to the address input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must be pulled low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading.
3
SP5769
byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Read mode When the device is in read mode, the status byte read from the device takes the form shown in Table 3. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic `1' if the VCC supply to the device has dropped below 3V (at 25C ), e.g. when the device is initially turned on. The POR is reset to `0' when the read sequence is terminated by a STOP command. When POR is set high this indicates the programmed information may be corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic'1'is present if the device is locked, and a logic `0' if it is not.
R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Division ratio 2 4 8 16 32 64 128 256 24 5 10 20 40 80 160 320
Table 1 Reference division ratios
Write mode With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Bytes 4 and 5 control the reference divider ratio (see Table 1), charge pump setting (see Table 6), REF/COMP output (see Table 7), output ports and test modes (see Table 5). After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic `0' indicating byte 2, and a logic `1' indicating byte 4. Having interpreted this byte as either byte 2 or 4, the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous MSB 1 0 27 1 C1
Programable features
G RF programmable divider Function as described
above.
G Reference programmable divider Function as
described above.
G Charge pump current The charge pump current can
be programmed by bits C1 and C0 within data byte 5, as defined in Table 6. G Test mode The test modes are invoked by setting bit T2 = 1, with selected test modes as defined by bits T1 and T0 as described in Table 5. Clock input on crystal and RF input pins are required to invoke FL test modes. G Reference/Comparison frequency output The reference frequency fREF or comparison frequency fCOMP can be switched to the REF/COMP output, function as defined in Table 7. RE and RS default to logic'1'during device power up, thus enabling the comparison frequency fCOMP at the REF/COMP output. LSB 0 28 20 R0 P0
Address Programmable divider Programmable divider Control data Control data
1 214 26 T2 C0
0 213 25 T1 RE
0 212 24 T0 RS
0 211 23 R3 P3
MA1 210 22 R2 P2
MA0 29 21 R1 P1
A A A A A
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Table 2 Write data format (MSB transmitted first)
A MA1, MA0 214-20 R3-R0 C1, C0 RE RS T2-T0 P3-P0
Acknowledge bit Variable address bits (see Table 4) Programmable division ratio control bits Reference division ratio select (see Table 1) Charge pump current select (see Table 6) Reference oscillator output enable REF/COMP output select when RE=1 (see Table 7) Test mode control bits (see Table 5) P3, P2, P1 and P0 port output states
4
SP5769
MSB 1 POR LSB 1 0
Address Status byte
1 FL
0 0
0 0
0 0
MA1 0
MA0 0
A A
Byte 1 Byte 2
Table 3 Read data format (MSB transmitted first)
A MA1, MA0 POR FL MA1 0 0 1 1 MA0 0 1 0 1
Acknowledge bit Variable address bits (see Table 4) Power On Reset indicator Phase lock flag T2 0 1 1 1 1 T1 X 0 0 1 1 T0 X 0 1 0 1 Test mode description Normal operation Charge pump sink Status byte FL = logic `0' Charge pump source Status byte FL = logic `0' Charge pump disable Status byte FL = logic `1' P0 = fPD/2
Address input voltage level 0 to 0*1VCC Open circuit 0*4VCC to 0*6VCC * 0*9VCC to VCC
* Programmed by connecting a 15k resistor from pin 10 to VCC
Table 4 Address selection
Current (A) C1 0 0 1 1 C0 Min. 0 1 0 1 6116 6247 6517 61087 Typ. 6155 6330 6690 61450 Max. RE 6194 6412 6862 61812 0 1 1 RS X 0 1
Table 5 Test modes
REF/COMP output High impedance fREF selected fCOMP selected
Table 6 Charge pump current
Table 7 REF/COMP output
300
VIN (mVRMS INTO 50)
100
OPERATING WINDOW
40
100 200
1000
2000 FREQUENCY (MHz)
3000
4000
Figure 3 Typical RF input sensitivity
5
SP5769
j1 j0.5 j2
j0.2 j5
0
0.2
0.5
1
2
5 0*5GHz 1GHz 2j5
2j0.2
1*5GHz 2*5GHz 2j0.5 2j2 2j1
S11: ZO = 50 Normalised to 50
Figure 4 RF input impedance
2 68p 150p 3 SP5769
Figure 5 Crystal oscillator application
Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21
Value/type 18pF 2*2nF 68pF 1nF 1nF 10nF 100nF 4*7F 100nF 100pF 1nF 100pF 100pF 4*7nF 100pF 4*7F 10nF 39pF 100pF 1nF 1nF
Component C22 C23 C24 LED 1 LED 2 R1 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 S1 T1 VCO X1
Value/type 100pF 4*7F 1nF HLMPK-150 HLMPK-150 4*7k 4*7k 4*7k 4*7k 13*3k 22k 1k 0 16 16 16 68 SW DIP-2 BCW31 POS_2000 4MHz
Table 8 Component values for Figure 6
6
J1 POWER CONNECTOR 15V VCC C7 130V C9 18V 130V C3 R8 R9 T1
1 16 15 14 13 12 11 10 9 2 3 4 5 1
C16
2 3
C8 C23
4 5
RF2 EXT REF
C22
C2 C6 R7 C1 X1 C18 C5 C4 VCC C10 ADD CON1
8
R10 C14 R11 R12 C20 R13
J2 VARACTOR
2 1
VCC
RF INPUT 18V RF1 C19
VT
VCO
J5 SP 5769
SDA5 18V LED1 LED2 LED3 LED4 C24 LK1 J4 R6 R5 R4
7
3
5V R1 S1
6
4
Figure 6 SP5769 evaluation board
C17
43 2 1
5
VCO tuning range = 1370MHz to 2000MHz C21
RF OUT
SCL5
6
C15
C13
C12
R14
RF3 COMP OUTPUT PORT OUTPUTS
SP5769
7
SP5769
Top view
Bottom view Figure 7 SP5769 evaluation board layout
8
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